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km29w16000at, KM29W16000AIT flash memory 1 document title 2m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 1.1 remark preliminary final history initial issue. data sheet 1998. draft date april 10th 1998 july 14th 1998
km29w16000at, KM29W16000AIT flash memory 2 2m x 8 bit nand flash memory the km29w16000a is a 2m(2,097,152)x8bit nand flash memory with a spare 64k(65,536)x8bit. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation programs the 264-byte page in typically 250 m s and an erase operation can be performed in typ- ically 2ms on a 4k-byte block. data in the page can be read out at 80ns cycle time per byte. the i/o pins serve as the ports for address and data input/out- put as well as command inputs. the on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verify and margin- ing of data. even the write-intensive systems can take advan- tage of the km29w16000a extended reliability of 1,000,000 program/erase cycles by providing either ecc(error correction code) or real time mapping-out algorithm. these algorithms have been implemented in many mass storage applications and also the spare 8bytes of a page combined with the other 256 bytes can be utilized by system-level ecc. the km29w16000a is an optimum solution for large nonvolatile storage application such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility. general description features voltage supply : 2.7v ~ 5.5v organization - memory cell array : (2m + 64k)bit x 8bit - data register : (256 + 8)bit x8bit automatic program and erase - page program : (256 + 8)byte - block erase : (4k + 128)byte - status register 264-byte page read operation - random access : 10 m s(max.) - serial page access : 80ns(min.) fast write cycle time - program time : 250 m s(typ.) - block erase time : 2ms (typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 1m program/erase cycles - data retention : 10 years command register operation 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) - forward type pin configuration v ss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc q i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c gnd r/ b re ce v cc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) standard type note : connect all v cc ,vccq and v ss pins of each device to power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o0 ~ i/o7 data inputs/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect gnd ground input r/ b ready/busy output v cc power(2.7v~5.5v) v cc q output butter power(2.7v~5.5v) v ss ground n.c no connection pin description
km29w16000at, KM29W16000AIT flash memory 3 256b column 8b column figure 1. functional block diagram figure 2. array organization note : a12 to a20 : block address * : x can be v il or v ih . i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 3rd cycle a 16 a 17 a 18 a 19 a 20 *x *x *x x-buffers 16m + 512k bit command nand flash array (256 + 8)byte x 8192 y-gating page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers a 8 - a 20 a 0 - a 7 command ce re we cle ale wp i/0 0 i/0 7 16m : 8k row (=512 block) 256byte 8 bit 8byte 1 block(=16 row) (4k + 128)byte i/o 0 ~ i/o 7 1 page = 264 byte 1 block = 264 b x 16 pages = (4k + 128) bytes 1 device = 264b x 16pages x 512 blocks = 16.5 mbits column address row address (page address) page register vccq vss
km29w16000at, KM29W16000AIT flash memory 4 product introduction the km29w16000a is a 16.5mbit(17,301,504 bit) memory organized as 8192 rows by 264 columns. spare eight columns are located from column address of 256 to 263. a 264-byte data register is connected to memory cell arrays accommodating data trans- fer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 16 pages formed by one nand structures, totaling 264 nand structures of 16 cells. the array organization is shown in figure 2. the program and read operations are executed on a page basis, while the erase operation is executed on block basis. the memory array consists of 512 separately or grouped erasable 4k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the km29w16000a. the km29w16000a has addresses multiplexed into 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o`s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. the 2m byte physical space requires 21 addresses, thereby requiring three cycles for byte-level addressing : co l- umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the km29w16000a. table 1. command sets function 1st. cycle 2nd. cycle acceptable command during busy sequential data input 80h - read 1 00h - read 2 50h - read id 90h - reset ffh - o page program 10h - block erase 60h d0h read status 70h - o
km29w16000at, KM29W16000AIT flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the path activation for address and input data to the internal address/data register. addresses are latched on the rising edge of we with ale high, and input data is latched when ale is low. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling ed ge of re which also increments the internal column address counter by one. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to outputs data during read operations. the i/o pins float to high -z when the chip is deselected or the outputs are disabled. write protect ( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and return to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or outputs are disabled. power line(v cc & v ccq ) the v ccq is the power supply for i/o interface logic. it is electrically isolated from main power line(v cc =2.7~5.5v) for supporting 5v tolerant i/o with 5v power supply at v ccq .
km29w16000at, KM29W16000AIT flash memory 6 dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions vcc=2.7v ~ 3.6v vcc=3.6v ~ 5.5v unit min typ max min typ max operating current sequential read i cc 1 tcycle=80ns, ce =v il , i out =0ma - 10 20 - 15 30 ma program i cc 2 - - 10 20 - 15 30 erase i cc 3 - - 10 20 - 25 40 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 5 50 - 5 50 m a input leakage current i li v in =0 to 5.5v - - 10 - - 10 output leakage current i lo v out =0 to 5.5v - - 10 - - 10 input high voltage v ih i/o pins 2.0 - v cc q+0.3 3.0 - v cc q+0.5 v except i/o pins 2.0 - v cc +0.3 3.0 - v cc +0.5 input low voltage, all inputs v il - -0.3 - 0.6 -0.3 - 0.8 output high voltage level v oh i oh =-400 m a 2.4 - - 2.4 - - output low voltage level v ol i ol =2.1ma - - 0.4 - - 0.4 output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - 8 10 - ma absolute maximum ratings note : 1. minimum dc voltage is -0.3v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc q+0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to +7.0 v temperature under bias km29w16000at t bias -10 to +125 c KM29W16000AIT -40 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5 ma recommended operating conditions (voltage reference to gnd, km29w16000at : t a =0 to 70 c, KM29W16000AIT : t a =-40 to 85 c) note : 1. vcc and vccq pins are separater each other. parameter symbol min typ. max unit supply voltage v cc 2.7 - 5.5 v supply voltage v cc q 1) 2.7 - 5.5 v supply voltage v ss 0 0 0 v
km29w16000at, KM29W16000AIT flash memory 7 capacitance (t a =25 c, vcc=5.0v f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. km29w16000a may or may not include bad blocks. bad blocks are defined as blocks that contain one or more bad bits.do not try to access these bad blocks for program and erase. the minimum valid blocks are guaranteed for 10 years data retention or 1m program erase cyclin g. (refer to the attached technical notes ) 2. the 1st block, which is placed on 00h block address, is guaranteed to be a good block parameter symbol min typ. max unit valid block number n vb 502 508 512 blocks program/erase characteristics parameter symbol min typ max unit program time t prog - 0.25 1.5 ms number of partial program cycles in the same page nop - - 10 cycles block erase time t bers - 2 10 ms mode selection note : 1. x can be v il or v ih 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x sequential read & data output l l l h h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by ac test condition (km29w16000at:t a =0 to 70 c, KM29W16000AIT:t a =-40 to 85 c, v cc =2.7v ~ 5.5v unless otherwise noted) parameter value vcc=2.7v ~ 3.6v vcc=3.6v ~ 5.5v input pulse levels 0.4v to 2.4v 0.4v to 3.4v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load 1 ttl gate and 1 ttl gate and cl = 100pf cl=50pf(3.0v+/-10%),100pf(3.0v~3.6v)
km29w16000at, KM29W16000AIT flash memory 8 ac characteristics for operation note : 1. if ce goes high within 30ns after the rising edge of the last re , r/ b will not return to v ol . 2. the time to ready depends on the value of the pull-up resistor tied r/ b pin. 3. to break the sequential read cycle, ce must be held high for longer time than t ceh . parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay t ar 150 - ns ale to re delay(read id) t ar1 200 - ns ce to re delay( id read) t cr 200 - ns ready to re low t rr 20 - ns we high to busy t wb - 200 ns read cycle time t rc 80 - ns re access time t rea - 45 ns re high to output hi-z t rhz 5 20 ns ce high to output hi-z t chz - 30 ns re high hold time t reh 20 - ns output hi-z to re low t ir 0 - ns last re high to busy(at sequential read) t rb - 200 ns ce high to ready(in case of interception by ce at read) (1) t cry - 100+tr(r/ b ) (2) ns ce high hold time(at the last serial read) (3) t ceh 250 - ns re low to status output t rsto - 45 ns ce low to status output t csto - 55 ns re high to we low t rhw 0 - ns we high to re low t whr 50 - ns device resetting time(read/program/erase) t rst - 5/10/500 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 20 - ns cle hold time t clh 40 - ns ce setup time t cs 20 - ns ce hold time t ch 40 - ns we pulse width t wp 40 - ns ale setup time t als 20 - ns ale hold time t alh 40 - ns data setup time t ds 30 - ns data hold time t dh 20 - ns write cycle time t wc 80 - ns we high hold time t wh 20 - ns
km29w16000at, KM29W16000AIT flash memory 9 identifying invalid block(s) in the km29w16000a invalid blocks km29w16000a technical notes all device locations are erased(ffh) prior to shipping. device with invalid block(s) will be randomly written with 00h data with in the first or second page in the invalid block(s). this page may or may not contain the invalid cell(s). the 00h data just marks the block(s) that contains the invalid cell(s). a system that can utilize these devices must be able to recognize invalid block(s) via the fo llowing suggested flow chart (figure 1). figure 1. flow chart to create invalid block table. start set : block = 0 check "ff" ? set : block n + 1 block = 511 ? end create (or update) invalid block(s) table no no yes yes the km29w16000a flash device may or may not contain up to 10 invalid blocks. invalid blocks are defined as blocks that contain one or more invalid bits. typically, an invalid block will contain a single bad bit. devices with invalid block(s) have the same quality levels as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the per for- mance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. the system d esign must be able to mask out the invalid block(s) via address mapping. the 1st block of the km29w16000a, however, is fully guarantee d to be a good block. * for the 1st or 2nd page *
km29w16000at, KM29W16000AIT flash memory 10 error in program or erase operation the device may fail during a program or erase operation. the following possible failure modes should be considered when implementing a highly reliable system. km29w16000a technical notes (continued) failure mode detection and countermeasure sequence block erase failure status read after erase --> block replacement page program failure status read after program --> block replacement single bit program failure ("1" --> "0") block verify after program --> retry or ecc ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection block replacement when the error happens in block "a", try to reprogram the data into another block "b" by reloading from an external buffer. then, prevent further system access to block "a"(by creating a "bad block" table or other appropriate scheme.) during program operation ; during erase operation ; when the error occurs after an erase operation, prevent future accesses to this bad block (again by creating a table within the system or other appropriate scheme.) buffer memory error occurs block a block b
km29w16000at, KM29W16000AIT flash memory 11 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 8 ~a 15 a 16 ~a 20 t cls t clh t ch t alh t wp t als t ds t dh t cs t cls t cs t wc t wc t wp t wh t wp t wh t als t ds t dh t dh t ds t dh t alh t wp t ds
km29w16000at, KM29W16000AIT flash memory 12 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 255 ale t clh t ch t als t wc t wp t wh t wp t ds t dh t ds t dh t ds t dh t wp * s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. dout dout dout t rc t rea t rea t rr t chz* t chz* t rea t reh ? ? ?
km29w16000at, KM29W16000AIT flash memory 13 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t cls t clh t cls t cs t wp t ch t whr t csto t chz* t rhz* t rsto t ir t dh t ds read1 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h a 0 ~ a 7 a 8 ~ a 15 a 16 ~ a 20 column address page(row) address t wb t ceh t chz t r t rc t rhz t rb t ar t rr t cry dout n+3 dout n+2 dout n+1 dout 263 dout n ? ? ?
km29w16000at, KM29W16000AIT flash memory 14 read1 operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h a 0 ~ a 7 a8 ~ a 15 a 16 ~ a 20 dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 8 ~ a 15 a 16 ~ a 20 dout dout 263 m address 255+m dout 255+m+1 selected row start address m 256 8 t ar t r t rr t wb ? ? ?
km29w16000at, KM29W16000AIT flash memory 15 sequential row read operation ce cle r/ b i/o 0 ~ 7 we ale re 00h a 0 ~ a 7 busy m output a 8 ~ a 15 a 16 ~ a 20 dout n dout n+1 dout n+2 dout 263 dout 0 dout 1 dout 2 dout 263 busy m+1 output n ready page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o0 din n din din 10h 263 n+1 a 0 ~ a 7 a 16 ~ a 20 a 8 ~ a 15 sequential data input command column address page(row) address 1 up to 264 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb ? ? ? ? ? ? ? ? ? ?
km29w16000at, KM29W16000AIT flash memory 16 block erase operation (erase one block) ce cle r/ b i/o 0 ~ 7 we ale re 60h a 16 ~ a 20 a 8 ~ a 15 auto block erase setup command erase command read status command i/o 0 =0 successful erase doh 70h i/o 0 busy t bers t wb block address i/o 0 =1 error in erase manufacture & device id read operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech note* t rea note* km29v16000 : eah km29n16000 : 64h km29w16000 : eah ?
km29w16000at, KM29W16000AIT flash memory 17 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o pera- tion. three types of operations are available : random read, sequential page read and sequential row read. the random read mode is enabled when the page address is changed. the 264 bytes of data within the selected page are trans- ferred to the data registers in less than 10 m s(t r ). the cpu can detect the completion of this data transfer(t r ) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 80ns cycle time by sequentially pulsing re with ce staying low. high to low transitions of the re clock output the data starting from the selected column address up to the last column address(column 264). after the data of last column address is clocked out, the next page is automatically selected for sequential read. waiting 10 m s again allows for reading of the page. the sequential row read operation is terminated by bringing ce to high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 256 t o 263 may be selectively accessed by writing the read2 command. addresses a 0 to a 2 set the starting address of the spare area while addresses a 3 to a 7 are ignored. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare eight bytes of each page may be sequentially read. the read1 command(00h) is needed to move the pointer back to the main area. figures 3 thru 6 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h a 0 ~ a 7 & a 8 ~ a 20 data output(sequential) (00h command) s eek time data field spare field ce cle ale r/ b we i/o 0 ~ 7 re t r
km29w16000at, KM29W16000AIT flash memory 18 figure 5. sequential row read1 operation figure 4. read2 operation 50h busy(seek time) a 0 ~ a 2 & a 8 ~ a 20 data output(sequential) spare field ce cle ale r/ b we data field spare field data field spare field 00h a 0 ~ a 7 & a 8 ~ a 20 i/o 0 ~ 7 r/ b start add.(3cycle) start add.(3cycle) data output data output data output 1st 2nd nth (264 byte) (264 byte) (a 3 ~ a 7 : don't care) 1st 2nd nth i/o 0 ~ 7 re s eek time t r t r t r ?
km29w16000at, KM29W16000AIT flash memory 19 figure 6. sequential row read2 operation page program the device is programmed basically on a page basis. but it also allows multiple partial page programming of a byte or consecutiv e bytes up to 264 may be programmed in a single page program cycle. the number of partial page programming operation in the same page without an intervening erase operation must not exceed ten. the addressing may be done in random order in a block. a page program cycle consist of a serial data loading period in which up to 264 bytes of data must be loaded into the device, and nonvo latile programming period in which the loaded data is programmed into the appropriate cell. the sequential data loading period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded. in order to program the bytes in the spare columns of 256 to 263, the pointer should be set to the spare area by writing the rea d 2 command(50h) to the command register. the pointer remains in the spare area unless the read 1 command(00h) is entered to retum to the main area. the page program confirm command(10h) initiates the programming process. writing 10h alone without perviously entering the serial data will not initiate the programming process. the internal write controller automatically execu tes the algorithms and timings necessary for program and verify, thereby freeing the cpu for other tasks. once the program process start s, the status register may be read re and ce low after the read status command(70h) is written to it. the cpu can detect the com- pletion of program cycle by monitoring the r/ b output, or the status bit(i/o 6 ) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0 ) may be checked(figure 7). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the c om- mand register remains in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 2 & a 8 ~ a 20 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (8byte) (8byte) data field spare field 1st 2nd nth (a 3 ~ a 7 : don't care) 1st figure 7. program & read status operation 80h a 0 ~ a 7 & a 8 ~ a 20 i/o 0 ~ 7 r/ b address & data input i/o 0 pass 264 byte data 10h 70h fail t r t r t r t prog ?
km29w16000at, KM29W16000AIT flash memory 20 figure 8. block erase operation block erase the erase operation is done on a block(4k byte) basis. block address loading is accomplished in two cycles initiated by an erase setup command(60h). only address a 12 to a 20 is valid while a 8 to a 11 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. when the erase operation is complete, the write status bit(i/o 0 ) may be checked. figure 8 details the sequence. 60h block add. : a 8 ~ a 20 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation is completed successfully. after writing 70h command to the command register, a read cycle output s the contents of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. sr status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table2. status register definition
km29w16000at, KM29W16000AIT flash memory 21 figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (note*) respectively. the command reg- ister remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h address. 1 cycle dout(ech) dout(note*) a 0 ~ a 7 :"0" maker code device code t cr t ar1 t rea note* km29v16000 : eah km29n16000 : 64h km29w16000 : eah figure 10. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. reset command is not necessary for normal operation. refer to figure 10 below. after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b table3. device status t rst
km29w16000at, KM29W16000AIT flash memory 22 ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. an appropriate pull-up resister is required for proper operation and the value may be calculated by the following equation. rp = v cc open drain output device gnd v cc (max.) - v ol (max.) i ol + s i l = note* 8ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. *note: km29v16000a : 3.2v km29n16000a : 5.1v km29w16000a : 5.1v when vcc=3.6v~5.5v 3.2v when vcc=2.7v~3.6v r/ b figure 11. ac waveforms for power transition data protection the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down as shown in figure 11. the two step command sequence for program/erase provides additional software protection. v cc wp high ? ?
km29w16000at, KM29W16000AIT flash memory 23 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

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